The present invention relates to the formation of damascene structures on a semiconductor wafer and especially to methods in which an organic film is utilized to protect the underlying dielectric material during etching of the damascene trench.
In damascene processing, the interconnect structure or wiring pattern is formed within a dielectric layer. Using known techniques a photoresist material is used to define the wiring pattern. The patterned photoresist acts as a mask through which a pattern of the dielectric material is removed by a subtractive etch process such as plasma etching or reactive ion etching. The etched openings are used to define wiring patterns in the dielectric layer. The wiring patterns are then filled with a metal using a filling technique such as electroplating, electroless plating, chemical vapor deposition, physical vapor deposition or a combination thereof. Excess metal can then be removed by chemical mechanical polishing through a process known as planarization.
In a single damascene process, via openings are provided in the dielectric layer and filled with a conducting metal, which is often referred to as metallization, to provide electrical contact between layers of wiring levels. In a dual damascene process, the via openings and the wiring pattern are both provided in the dielectric layer before filling with the conducting metal. Damascene processing followed by metallization is continued for each layer until the integrated circuit device is completed.
In the present processing of damascene structures, a so-called planarization material is used to fill the vias after the dielectric has been etched out. The planarization material also protects the vias during subsequent lithographic processing. A spin-on organic planarizing material (protective material) that is presently utilized is NFC 1400, available from JSR Corporation.
However, a problem with the use of spin-on organic planarizing material is that during the subsequent lithographic processing referred to above, the damascene structure can become oversized, undersized or otherwise nonconforming. The difficulties inherent in the use of the spin-on organic planarizing material are described below.
FIGS. 1A through 1G describe the conventional processing of damascene structures using a spin-on organic planarizing material. Referring to FIG. 1A, there is shown a semiconductor structure 10 being prepared for damascene structure. At this stage of the process, semiconductor structure 10 comprises semiconductor wafer 34, a previous wiring level which comprises dielectric 12, metallization 14 and capping layer 18, and the next wiring level which begins with dielectric 16. Dielectric 16 has been previously prepared by forming openings 20 therein by conventional lithographic and etching processing.
Referring now to FIG. 1B, spin-on organic planarizing material 22 is applied in the openings 20 and on the dielectric 16, followed by hard mask 24 (usually a low temperature oxide) and photoresist 26.
In FIG. 1C, the photoresist has been conventionally exposed and developed followed by definition of the hard mask 26 to form openings 28.
Thereafter, as shown in FIG. 1D, there is the spin-on organic planarizing material transfer etch in an H2+O2 plasma which removes the spin-on organic planarizing material 22 down to or slightly below the surface 30 of the dielectric 12.
Then, semiconductor structure 10 undergoes etching to remove dielectric 16 and enlarge openings 28. The dielectric 16 is etched by a combination of chemicals, for example CF4, C4F8, NF3, N2, O2, or NH3, using the spin-on organic planarizing material 22A as a mask, and at the same time the hard mask layer 24 is completely removed from the wafer to result in the structure shown in FIG. 1E. Note that spin-on organic planarizing material 22 still remains in the vias at this time.
Referring now to FIG. 1F, the remaining spin-on organic planarizing material 22, 22A is stripped using an H2+O2 plasma.
Lastly, capping layer 18 is opened using a combination of chemicals, for example CHF3, Ar, O2, N2, to result in the semiconductor structure shown in FIG. 1G.
The processing of semiconductor structure 10 as just described is the ideal structure. The structure as it appears in reality is often quite different. Referring now to FIGS. 2, 3, and 4, there is illustrated the reality of what often happens in the spin-on organic planarizing material transfer etch step of FIG. 1D. In FIG. 2A, the spin-on organic planarizing material transfer etch has caused undercutting of the spin-on organic planarizing material at 36 resulting in an oversized critical dimension (CD) as shown in FIG. 2B.
In FIG. 3A, the spin-on organic planarizing material transfer etch has insufficiently etched the spin-on organic planarizing material at 38 resulting in an undersized CD as shown in FIG. 3B.
In FIG. 4A, the spin-on organic planarizing material transfer etch has caused profile damage of the spin-on organic planarizing material at 40 resulting in profile damage to the semiconductor structure 10 as shown in FIG. 4B.
In view of the foregoing, it would be desirable to have an improved process wherein the spin-on organic planarizing material transfer etch step can be eliminated so that the resulting semiconductor structure does not have an oversized CD, undersized CD or profile damage.
Accordingly, it is a purpose of the present invention to have a process wherein the spin-on organic planarizing material transfer etch step is eliminated to avoid an oversized CD, undersized CD or profile damage.
It is another purpose of the present invention to have a process wherein the spin-on organic planarizing material transfer etch step is eliminated to result in a semiconductor structure which is more manufacturable.
These and other purposes of the invention will become more apparent after referring to the following description of the invention in conjunction with the accompanying drawings.